View A67L7332E-6_476042.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

A67L8316/A67L8318/ A67L7332/A67L7336 Series
256K X 16/18, 128K X 32/36 Preliminary
Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History
Rev. No.
0.0 0.1
LVTTL, Pipelined DBATM SRAM
History
Initial issue Change fast access time from 4.0/4.2/4.5/5.0 ns to 4.5/5.0/6.0 ns
Issue Date
March 11, 1999 December 29, 1999
Remark
Preliminary
PRELIMINARY
(December, 1999, Version 0.1)
AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
A67L8316/A67L8318/ A67L7332/A67L7336 Series
256K X 16/18, 128K X 32/36 Preliminary
Features
n Fast access time: 4.5/5.0/6.0 ns (117/100/83MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.3V 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Internally self-timed write cycle n Selectable BURST mode (Linear or Interleaved) n SLEEP mode (ZZ pin) provided n Available in 100 pin LQFP package
LVTTL, Pipelined DBATM SRAM
General Description
The AMIC Direct Bus AlternationTM (DBATM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during WriteRead alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2 , BW3 ,BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD is LOW. Parity/ECC bits are only available on the X18/36 version. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.
PRELIMINARY
(December, 1999, Version 0.1)
1
AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Pin Configuration
OE ADV/ LD
BW4
BW3
BW2
BW1
VCC
VSS
CE2
CE2
CEN
CLK
R/W
128K X 36/32
CE A6 A7
NC
NC
A8 A8 82
BW2
BW1
OE ADV/ LD
VCC
CE2
CE2
CEN
VSS
CLK
R/W
NC
NC
NC
NC
CE
256K X 18/16
A6 A7
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/Oc0/NC I/Oc1 I/Oc2 VCCQ VSSQ I/Oc3 I/Oc4 I/Oc5 I/Oc6 VSSQ VCCQ I/Oc7 I/Oc8 VCC VCC VCC VSS I/Od0 I/Od1 VCCQ VSSQ I/Od2 I/Od3 I/Od4 I/Od5 VSSQ VCCQ I/Od6 I/Od7 I/Od8/NC
NC NC NC VCCQ VSSQ NC NC I/Ob0 I/Ob1 VSSQ VCCQ I/Ob2 I/Ob3 VCC VCC VCC VSS I/Ob4 I/Ob5 VCCQ VSSQ I/Ob6 I/Ob7 I/Ob8/NC NC VSSQ VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
81 80 79 78 77 76 75 74 73 72 71 70 69
A9
A9
A17 NC NC VCCQ VSSQ NC I/Oa8/NC I/Oa7 I/Oa6 VSSQ VCCQ I/Oa5 I/Oa4 VSS VCC VCC ZZ I/Oa3 I/Oa2 VCCQ VSSQ I/Oa1 I/Oa0 NC NC VSSQ VCCQ NC NC NC
I/Ob8/NC I/Ob7 I/Ob6 VCCQ VSSQ I/Ob5 I/Ob4 I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 I/Ob0 VSS VCC VCC ZZ I/Oa8 I/Oa7 VCCQ VSSQ I/Oa6 I/Oa5 I/Oa4 I/Oa3 VSSQ VCCQ I/Oa2 I/Oa1 I/Oa0/NC
A67L8316E A67L8318E A67L7332E A67L7336E
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MODE MODE
VCC
NC
NC
NC
NC
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15 A15
VSS
A10
A1
A11
A12
A13
A14
VCC
VSS
A16
NC
NC
NC
NC
A5
A4
A3
A2
A0
A16
PRELIMINARY
(December, 1999, Version 0.1)
2
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Block Diagram (128K X 32/36)
ZZ MODE
MODE LOGIC
ADV/LD
CEN CLK
CLK LOGIC
BURST LOGIC ADDRESS COUNTER CLR
A0-A16
ADDRESS REGISTERS
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
8/9
BYTEa WRITE DRIVER BYTEb WRITE DRIVER BYTEc WRITE DRIVER BYTEd WRITE DRIVER
8/9
8/9 ADV/LD R/W BWE BW1 BW2 BW3 BW4 WRITE REGISTRY & CONTROL LOGIC
8/9
128KX8/X9X4 MEMORY SENSE AMPS
8/9
8/9 ARRAY
OUTPUT REGISTERS & OUTPUT BUFFERS
I/Os
8/9
8/9
DATA-IN REGISTERS
DATA-IN REGISTERS
CE CE2 CE2
CHIP ENABLE LOGIC
PIPELINED ENABLE LOGIC
OUTPUT ENABLE LOGIC
OE
PRELIMINARY
(December, 1999, Version 0.1)
3
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Block Diagram (256K X 16/18)
ZZ MODE
MODE LOGIC
ADV/LD
CEN CLK
CLK LOGIC
BURST LOGIC ADDRESS COUNTER CLR
A0-A17
ADDRESS REGISTERS
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
8/9 ADV/LD R/W BWE BW1 BW2 WRITE REGISTRY & CONTROL LOGIC
BYTEa WRITE DRIVER
8/9 256KX8/X9X2 MEMORY SENSE AMPS OUTPUT REGISTERS & OUTPUT BUFFERS I/OS
8/9
BYTEb WRITE DRIVER
8/9
ARRAY
DATA-IN REGISTERS
DATA-IN REGISTERS
CE CE2 CE2
CHIP ENABLE LOGIC
PIPELINED ENABLE LOGIC
OUTPUT ENABLE LOGIC
OE
PRELIMINARY
(December, 1999, Version 0.1)
4
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Pin Description
Pin No. LQFP (X16/X18) 37 36 35,34,33,32, 100,99,82,81, 44,45,46,47, 48,49,50 80 93 (BW1) 94 (BW2 ) LQFP (X32/X36) 37 36 35,34,33,32, 100,99,82,81, 44,45,46,47, 48,49,50 A0 A1 A2 - A16 Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for higher-density 9Mb and 18Mb DBA SRAMs, respectively. A0 and A1 are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; BW4 controls I/Od pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock are rising edge. Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/LD LOW). Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion. Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion. Output Enable : This active low asynchronous input enables the data I/O output drivers. Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/ W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. Symbol Description
A17 93 (BW1) 94 (BW2 ) 95 ( BW3 ) 96 (BW4 )
BW1 BW2 BW3 BW4
89
89
CLK
98
98
CE
92
92
CE2
97
97
CE2
86
86
OE
85
85
ADV/LD
PRELIMINARY
(December, 1999, Version 0.1)
5
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Pin Description (continued)
Pin No. LQFP (X16/X18) 87 LQFP (X32/X36) 87
CEN
Symbol
Description
Synchronous Clock Enable : This active low input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Snooze Enable : This active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. Read/Write : This active input determines the cycle type when ADV/LD is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. SRAM Data I/O : Byte "a" is I/Oa pins; Byte "b" is I/Ob pins; Byte "c" is I/Oc pins; Byte "d" is I/Od pins. Input data must meet setup and hold times around CLK rising edge.
64
64
ZZ
88
88
R/ W
(a) 58, 59, 62, 63, 68, 69, 72, 73 (b) 8,9,12,13, 18, 19, 22,23
(a) 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 (c) 2, 3, 6, 7, 8, 9, 12, 13, (d) 18, 19, 22, 23, 24, 25, 28, 29 51 80 1 30 31
I/Oa I/Ob I/Oc I/Od
74 24
NC/I/Oa NC/I/Ob NC/I/Oc NC/I/Od MODE
No Connect/Data Bits : On the X16/32 version, these pins are no connect (NC) and can be left floating or connected to GND to minimize thermal impedance. On the X18/36 version, these bits are I/Os. Mode : This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. No Connect : These pins can be left floating or connected to GND to minimize thermal impedance.
31
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 83, 84, 95, 96
38,39,42,43 83,84
NC
PRELIMINARY
(December, 1999, Version 0.1)
6
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Pin Description (continued)
Pin No. LQFP (X16/X18) 15, 41, 65, 91 LQFP (X32/X36) 15, 41, 65, 91 VCC Power Supply : See DC Electrical Characteristics and Operating Conditions for range. These pins do not have to be connected directly to VCC as long as the input voltage is VIH. This input is not connected to VCC bus internally. Isolated Output Buffer Supply : See DC Electrical Characteristics and Operating Conditions for range. Ground : GND. Isolated Output Buffer Ground Symbol Description
14, 16, 66
14, 16, 66
VCC
4, 11, 20, 27, 54, 61, 70, 77 17, 40, 90 5,10,21,26, 55,60,71,76
4, 11, 20, 27, 54, 61, 70, 77 17, 40, 90 5,10,21,26, 55,60,71,76
VCCQ
VSS VSSQ
PRELIMINARY
(December, 1999, Version 0.1)
7
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Truth Table (Notes 5 - 7)
Operation Address Used None
CE CE2 CE2
ZZ
Deselected Cycle, H X X L X X X L LH High-Z Power-down Deselected Cycle, None X H X L L X X X L LH High-Z Power-down Deselected Cycle, None X X L L L X X X L LH High-Z Power-down Continue Deselect None X X X L H X X X L LH High-Z 1 Cycle READ Cycle External L L H L L H X L L LH Q (Begin Burst) READ Cycle Next X X X L H X X L L LH Q 1,7 (Continue Burst) NOP/Dummy READ External L L H L L H X H L LH High-Z 2 (Begin Burst) Dummy READ Next X X X L H X X H L LH High-Z 1,2,7 (Continue Burst) WRITE Cycle External L L H L L L L X L LH D 3 (Begin Burst) WRITE Cycle Next X X X L H X L X L LH D 1,3,7 (Continue Burst) NOP/WRITE Abort None L L H L L L H X L LH High-Z 2,3 (Begin Burst) WRITE Abort Next X X X L H X H X L LH High-Z 1,2,3,7 (Continue Burst) IGNORE Clock Edge Current X X X L X X X X H LH 4 (Stall) SLEEP Mode None X X X H X X X X X X High-Z Notes: 1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE Abort means a WRITE command is given, but no operation is performed. 3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements. 4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BW1,BW2 , BW3 and BW4 ) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BW1enables WRITEs to Byte "a" (I/Oa pins); BW2 enables WRITEs to Byte "b" (I/Ob pins); BW3 enables WRITEs to Byte "c" (I/Oc pins); BW4 enables WRITEs to Byte "d" (I/Od pins). 7. The address counter is incremented for all Continue Burst cycles.
ADV/ LD L
R/ W
BWx
OE
CEN
CLK
I/O
Notes
PRELIMINARY
(December, 1999, Version 0.1)
8
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Partial Truth Table for READ/WRITE Commands (X16/X18)
Operation READ WRITE Byte "a" WRITE Byte "b" WRITE all bytes WRITE Abort/NOP R/ W H L L L L
BW1 BW2
X L H L H
X H L L H
Note : Using and BYTE WRITE(s), any one or more bytes may be written.
Partial Truth Table for READ/WRITE Commands (X32/X36)
Operation READ WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE all bytes WRITE Abort/NOP R/ W H L L L L L L
BW1 BW2 BW3 BW4
X L H H H L H
X H L H H L H
X H H L H L H
X H H H L L H
Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written.
Linear Burst Address Table (MODE = LOW)
First Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 Second Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 Third Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 Fourth Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 Second Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 Third Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 Fourth Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
PRELIMINARY
(December, 1999, Version 0.1)
9
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature (Topr) . . . . . . . . . . . 0C to 70C Storage Temperature (Tbias) . . . . . . . . . . -10C to 85 C Storage Temperature (Tstg) . . . . . . . . . . -55C to 125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics and Operating Conditions
(0C TA 70C, VCC, VCCQ = +3.3V 5% unless otherwise noted) Symbol VIH VIL ILI ILO Parameter Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current 0V VIH VCC Output(s) disabled, 0V VIN VCC VOH VOL VCC VCCQ Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply IOH = -4.0mA IOL = 8.0mA 3.135 3.135 2.4 0.4 3.465 VCC V V V V 1,4 1,4 1 1,5 Conditions Min. 2.0 -0.3 -1.0 -1.0 Max. VCC+0.3 0.8 1.0 1.0 Unit V V A A Note 1,2 1,2 3
Capacitance
Symbol CI CO CA Parameter Control Input Capacitance Input/Output Capacitance (I/O) Address Capacitance Conditions TA = 25C; f = 1MHz VCC = 3.3V Typ. 3 4 3 Max. 4 5 3.5 Unit pF pF pF Note 6 6 6
Note : 1. All voltages referenced to VSS (GND). 2. Overshoot : VIH +4.6V for t tKHKH/2 for I 20mA Undershoot : VIL -0.7V for t tKHKH/2 for I 20mA Power-up : VIH +3.456V and VCC 3.135V for t 200ms 3. MODE pin has an internal pull-up and exhibits an input leakage current of 10A. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VCC and VCCQ can be externally wired together to the same power supply. 6. This parameter is sampled.
PRELIMINARY
(December, 1999, Version 0.1)
10
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
ICC Operating Condition and Maximum Limits
Max. Symbol Parameter -4.5 -5 -6 Unit Conditions Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VCC = MAX; Outputs open Device selected; VCC = MAX; CEN VIH; All inputs VSS+0.2 or VCC-0.2; Cycle time tKC (MIN) Device deselected; VCC = MAX; All inputs VSS+0.2 or VCC-0.2; All inputs static; CLK frequency=0 Device deselected; VCC = MAX; All inputs VIL; or VIH; All inputs static; CLK frequency=0 Device deselected; VCC = MAX; All inputs VSS+0.2 or VCC-0.2; Cycle time tKC (MIN) ZZ VIH
ICC
Power Supply Current : Operating
300
250
230
mA
ICC1
Power Supply Current : Idle
12
10
8
mA
ISB2
CMOS Standby
10
10
10
mA
ISB3
TTL Standby
25
25
25
mA
ISB4
Clock Running
65
60
60
mA
ISB2Z
SLEEP Mode
10
10
10
mA
PRELIMINARY
(December, 1999, Version 0.1)
11
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
AC Characteristics (Note 4)
(0C TA 70C, VCC = 3.3V 5%) -4.5 Symbol Clock tKHKH tKF tKHKL tKLKH Clock cycle time Clock frequency Clock HIGH time Clock LOW time 8.5 3.4 3.4 117 10 3.5 3.5 100 12 4.0 4.0 83 ns MHz ns ns Parameter Min. Max. Min. -5 Max. Min. -6 Max. Unit Note
Output Times tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z
OE to output valid OE to output in Low-Z OE to output in High-Z
1.5 1.5 1.5 0 -
4.5 4.5 4.5 4.5
1.5 1.5 1.5 0 -
5.0 5.0 5.0 5.0
1.5 1.5 1.5 0 -
6.0 6.0 6.0 6.0
ns ns ns ns ns ns ns 1,2,3 1,2,3 4 1,2,3 1,2,3
Setup Times tAVKH tEVKH tCVKH tDVKH Address Clock enable ( CEN ) Control signals Data-in 2.0 2.0 2.0 1.7 2.2 2.2 2.2 2.0 2.5 2.5 2.5 2.5 ns ns ns ns 5 5 5 5
Hold Times tKHAX tKHEX tKHCX tKHDX Address Clock enable ( CEN ) Control signals Data-in 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.0 1.0 1.0 1.0 ns ns ns ns 5 5 5 5
Notes: 1. This parameter is sampled. 2. Output loading is specified with C1=5pF as in Figure 2. 3. Transition is measured 200mV from steady state voltage. 4. OE can be considered a "Don't Care" during WRITE; however, controlling OE can help fine-tune a system for turnaround timing. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADV/LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/LD is LOW) to remain enabled.
PRELIMINARY
(December, 1999, Version 0.1)
12
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 1.5ns 1.5V 1.5V See Figures 1 and 2
+3.3V Q Q ZO=50 50 351 5pF 317
VT=1.5V
Figure 1 Output Load Equivalent
Figure 2 Output Load Equivalent
PRELIMINARY
(December, 1999, Version 0.1)
13
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
SLEEP Mode
SLEEP Mode is a low current "Power-down" mode in which the device is deselected and current is reduced to ISB2Z. This duration of SLEEP Mode is dictated by the length of time the ZZ is in a HIGH state. After entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time tZZI is met, Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during tRZZ, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V5%) Symbol ISB2Z tZZ tRZZ tZZI tRZZI Parameter Current during SLEEP Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ VIH Min. 0 0 0 Max. 10 2(tKHKH) 2(tKHKH) 2(tKHKH) Unit mA ns ns ns ns 1 1 1 1 Note
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
tZZ tRZZ
ZZ
tZZI
ISUPPLY
IISB2Z tRZZI
ALL INPUTS (except ZZ)
DESELECT or READ Only
Output (Q)
High-Z
: Don't Care
PRELIMINARY
(December, 1999, Version 0.1)
14
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
READ/WRITE Timing
1 CLK tEVKH CEN tCVKH CE ADV/ LD R/W tKHCX tKHEX tKHKL tKLKH 2 tKHKH 3 4 5 6 7 8 9 10
BWx
ADDRESS tAVKH
A1 tKHAX
A2
A3
A4 tKHQV
A5
A6
A7
tDVKH I/O D(A1)
tKHDX D(A2)
tKHQX1 D(A2+1)
tKHQX Q(A3)
tGLQV Q(A4) tGHQZ tGLQX
Q(A4+1)
tKHQZ D(A5) tKHQX Q(A6)
OE COMMAND BURST WRITE D(A2+1) READ Q(A4) BURST READ Q(A4+1)
WRITE D(A1)
WRITE D(A2)
READ Q(A3)
WRITE D(A5)
READ Q(A6) : Don't Care
WRITE D(A7)
DESELECT
: Undefined
Note : 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register.
PRELIMINARY
(December, 1999, Version 0.1)
15
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
NOP, STALL and Deselect Cycles
1 CLK 2 3 4 5 6 7 8 9 10
CEN
CE ADV/ LD R/W
BWx
ADDRESS
A1
A2
A3
A4
A5 tKHQZ
I/O
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5) tKHQX
COMMAND
WRITE D(A1)
READ Q(A2)
STALL
READ Q(A3)
WRITE D(A4)
STALL
NOP
READ Q(A5) : Don't Care
CONTINUE DESELECT DESELECT : Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a "pause." A WRITE
is not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
PRELIMINARY
(December, 1999, Version 0.1)
16
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Ordering Information
Part No. A67L8316E-4.5 A67L8316E-5 A67L8316E-6 A67L8318E-4.5 A67L8318E-5 A67L8318E-6 A67L7332E-4.5 A67L7332E-5 A67L7332E-6 A67L7336E-4.5 A67L7336E-5 A67L7336E-6 128K X 36 128K X 32 256K X 18 256K X 16 Configure Cycle Time / Access Time 8.5ns / 4.5ns 10ns / 5ns 12ns / 6ns 8.5ns / 4.5ns 10ns / 5ns 12ns / 6ns 8.5ns / 4.5ns 10ns / 5ns 12ns / 6ns 8.5ns / 4.5ns 10ns / 5ns 12ns / 6ns 100L LQFP 100L LQFP 100L LQFP 100L LQFP Package
PRELIMINARY
(December, 1999, Version 0.1)
17
AMIC Technology, Inc.
A67L8316/A67L8318/ A67L7332/A67L7336 Series
Package Information LQFP 100L Outline Dimensions
unit: inches/mm
HE E
80 51
A2
A1 y D
81
50
HD D
100
31
1
30
e
b
c
Symbol A1 A2 b c HE E HD D e L L1 y
Dimensions in inches Min. 0.002 0.053 0.011 0.005 0.860 0.783 0.624 0.547 Nom. 0.055 0.013 0.866 0.787 0.630 0.551 0.026 BSC 0.018 0.024 0.039 REF 0 3.5 0.004 7 0.030 Max. 0.057 0.015 0.008 0.872 0.791 0.636 0.555
Dimensions in mm Min. 0.05 1.35 0.27 0.12 21.85 19.90 15.85 13.90 Nom. 1.40 0.32 22.00 20.00 16.00 14.00 0.65 BSC 0.45 0.60 1.00 REF 0 3.5 0.1 7 0.75 Max. 1.45 0.37 0.20 22.15 20.10 16.15 14.10
Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
L
L1
PRELIMINARY
(December, 1999, Version 0.1)
18
AMIC Technology, Inc.

▲Up To Search▲

Price & Availability of A67L7332E-6

	To Download A67L7332E-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .